ETISS-based Software Performance Simulator

The ETISS performance simulator evaluates the performance of embedded software (SW) programs and as such well-suited for rapid design space exploration (DSE). The simulator allows the user to execute target-compiled (e.g. for RISC-V) embedded SW on a host computer at high simulation speeds. Based on data from the SW execution, a performance estimator provides an accurate estimate of the SW's performance. Using provided code generators, the simulator can quickly be adapted to new target architectures, and thus offers a high level of flexibility required for effective DSE.

The ETISS performance simulator expands the existing ETISS instruction set simulator (ISS) through a performance estimator. During simulation, ETISS forwards observed data to the performance estimator. Based on this trace, the estimator calculates the performance of the target SW. To adapt the performance estimator to new target architectures, the M2ISAR-Perf code generator can be used. It receives a simple description of the targeted microarchitecture (CorePerfDSL) as input. Based on this, it generates the target-specific code in the form of so-called scheduling functions, which are then provided to the performance estimator. In addition, the ETISS performance simulator provides a generic memory model. This model can be configured via an ini-file to model the effect of different memory architectures on the target-SW's performance.

The ETISS performance simulator is currently supporting the Linux operating system.

The ETISS performance simulator targets companies that develop embedded software or systems with strict requirements that require advanced design space exploration.

The ETISS performance simulator will be open source under the Apache license.