Abstraction level
Implementation, Design, Analysis
Use Case Tasks
· UC#0001 - Specify Time Budgets
· UC#0002 - Specify Mode Dependent Timing Information
· Capture, Analyze, and Utilize Worst Case Timing Information
· Perform timing analysis on code level
Covered aspect
The Clock Constraint Specification Language (CCSL) provides expressions and relations to specify the time requirements and causal dependencies of multiclock systems. It was initially proposed, in the context of MARTE profile. CCSL is a mean to specify relations between the evolutions of some clocks or events. These relations can either be synchronous or asynchronous. A description of the language can be found in the deliverable TIMMO-2-USE_D1.3_SOTA.doc in paragraph 3.5.
TimeSquare is the software environment to deal with MARTE time model and CCSL. TimeSquare is an Eclipse plug-in that has four main functionalities:
1) interactive specifications
2) clock constraint checking,
3) generation of a solution,
4) displaying and exploring waveforms.
A wizard is included in TimeSquare. It facilitates clock definitions, clock constraint specifications, model element browsing, and parameter setting.
The second functionality checks constraint sanity and is called when the above mentioned wizard is not used.
The third functionality relies on a constraint solver that yields a satisfying execution trace or issues an error message in case of inconsistency.
The traces are given as waveforms written in VCD format. VCD (Value Change Dump) is an IEEE standard textual format for dump files used by EDA logic simulation tools.
Waveforms can be displayed with any VCD viewer. TimeSquare has its own viewer enriched with interactive constraint highlighting and access facilities.
Algorithm
The solver intensively uses Binary Decision Diagrams (BDD) to manipulate boolean equations induced by CCSL clock constraints.
Inputs
CCSL specification
Particular constraints on inputs
None
Preparation of input
A wizard is included in TimeSquare. It facilitates clock definitions, clock constraint specifications, model element browsing, and parameter setting.
Invocation of the algorithm
By starting the Timesquare tool framework, loading a project file, and writing CCSL specification. In a second step we check .constraint sanity. The next step is to run the simulator.
Outputs
Each run on the simulator yields a satisfying execution trace or issues an error message in case of inconsistency.
The traces are given as waveforms written in VCD format. VCD (Value Change Dump) is an IEEE standard textual format for dump files used by EDA logic simulation tools.
Visualization of results
Waveforms can be displayed with any VCD viewer. TimeSquare has its own viewer enriched with interactive constraint highlighting and access facilities. |