Tool Mentor: UPB Restbus Simulation
The UPB restbus simulator is implemented in SystemC. Restbus simulation can be aligned to the task simulation/analysis within the TIMMO-2-USE methodology.
The restbus simulation (RBS) is particularly applied during the early design phase of automotive hardware and software development to test and validate individual physical components within a partly virtualized environment. In our RBS, bus messages between physical network nodes and a virtual restbus (simulated ECUs) are exchanged and analyzed. In a HiL-like environment, one or more PCs are connected to a FlexRay network topology.
The objective of the RBS is to test and validate the functionality of the model under test by means of simulation.
Relationships
Main Description

Abstraction level

Design

Use Case Tasks

·         UC#0010 - Specify Synchronization Timing Constraints

·         UC#0007 - Develop Application and Infrastructure

·         UC#0005 - Develop Control Applications

·         UC#0012 - Integrate Re-usable Component

Covered aspect

Worst and best seen cases and statistics - Simulation  

Algorithm

Restbus simulation and Synchronization

Inputs

Source code for the behavior of the SWCs together with their timing information + Hardware device description

Particular constraints on inputs

none

Preparation of input

The behavior (C-code) of a software component under test can either be hand-written or generated using a behavior modeling tool like Matlab/Simulink or TargetLink. Afterwards it is integrated into a SystemC module

Invocation of the algorithm

Simulator as activated via command line.

Outputs

Simulation traces of bus traffic (communication data). This can be used for timing analysis

 

Visualization of results

In the case of the SystemC based Restbus simulator VCD traced files can be viewed offline using wave viewer tool like the GTKWave.