Tool Mentor: dSpace System TimeLine Analyzer
System TimeLine Analyzer is new tool and an add-on to the SystemDesk. It provides a graphical view of the system timing information as specified by AUTOSAR 4.0.3 standard and the actual timing information measured or gathered from the simulation runs, i.e., from “dSPACE Offline Simulator Player”.
Note: the tool “System TimeLine Analyzer” is under concept development.
Relationships
Main Description

Abstraction level

Implementation and Operational

Use Case Tasks

·         Tracing system behavior using relevant events

·         Analyzing measured timing data of the system

·         Validating of system timing behavior against existing timing requirements

Covered aspect

Tracing of system behavior using events occurred during RTE communication, and upon task invocation, preemptions, and network communication.

Analyzing measured timing data of the system and its validation against predefined timing requirements.

Algorithm

Instrumentation of RTE code and BSW modules to trace events during simulation

Inputs

Simulatable AUTOSAR system model, i.e., SystemDesk project file

Particular constraints on inputs

The global timing requirements must be available in AUTOSAR 4.0.3 format

Note: The timing information gathered from simulation runs must be in a particular format, i.e., dSPACE proprietary format, readable by System TimeLine Analyzer

Preparation of input

Load an AUTOSAR model in SystemDesk workspace, and create the “Simulation System”. Select the instrumentation point in RTE and BSW code to log the system behavior along timeline. For further processing, generate Virtual Processing Units (VPUs) i.e., one for each Ecu, to simulate the system behavior using dSPACE Offline Simulator. The system behavior is then recorded during the simulation runs that can be later visualized using SystemDesk TimeLine Analyzer.

Invocation of the algorithm

Load event trace log file generated during the simulation runs into the System TimeLine Analyzer

Outputs

Event trace log file containing RTE communication, task invocations and preemptions,

Visualization of results

Graphical visualization of the task scheduling and communication along the time axis and a list of validation errors, e.g., unconsumed   write access, oversampled read access, violations of timing requirements, etc.