Abstraction level
Design
Use Case Tasks
· UC#0010 - Specify Synchronization Timing Constraints
· UC#0007 - Develop Application and Infrastructure
· UC#0005 - Develop Control Applications
· UC#0012 - Integrate Re-usable Component
Covered aspect
Worst and best seen cases and statistics - Simulation
Algorithm
Restbus simulation and Synchronization
Inputs
Source code for the behavior of the SWCs together with their timing information + Hardware device description
Particular constraints on inputs
none
Preparation of input
The behavior (C-code) of a software component under test can either be hand-written or generated using a behavior modeling tool like Matlab/Simulink or TargetLink. Afterwards it is integrated into a SystemC module
Invocation of the algorithm
Simulator as activated via command line.
Outputs
Simulation traces of bus traffic (communication data). This can be used for timing analysis
Visualization of results
In the case of the SystemC based Restbus simulator VCD traced files can be viewed offline using wave viewer tool like the GTKWave. |